The invention is related to the field of capacitors used in uninterruptible power supplies and similar power systems.
Large capacitors are used in power supplies to provide desired filtering and hold-up of DC bus voltages under transient conditions. It is common to employ a "bank" of several such capacitors connected in parallel in order to achieve a large aggregate capacitance value. The parallel connections among the capacitors are often achieved using conductive "buses" having large current-carrying capacities. For example, two closely-spaced buses may run along a capacitor bank, one bus carrying a ground connection, for example, and the other carrying an output DC voltage connection, such as for example 800 volts DC. The parallel connection is achieved by connecting one bus to one terminal of each capacitor, and the other bus to the other terminal of each capacitor. In one common arrangement the buses are separate layers of a multi-layer planar bus structure.
When multiple cylindrical capacitors are used in a capacitor bank, it is desirable that they be placed in an upright position with respect to the bus structure in order to maximize packaging density, i.e., to realize the greatest amount of capacitance in a given space. However, the capacitors typically have their two terminals located at different ends of the capacitor body. The upper capacitor terminal must be connected to the respective bus in the multi-layer structure located at the other end of the capacitor. In prior systems, this connection has been made using a low-gauge wire running alongside the capacitor body from the upper terminal to the respective bus. Unfortunately, such a wire introduces additional inductance in the electrical path between the capacitor and the buses, increasing the amplitude of voltage spikes experienced by switching devices connected to the buses. It would be desirable to significantly reduce such inductance without sacrificing the spatial density achieved with the upright mounting of capacitors in a capacitor bank.